The present invention relates to a switching power source device and a switching power source control circuit including a series resonant circuit which has a current resonant inductor and a current resonant capacitor, and in particular relates to a switching power source device and a switching power source control circuit which eliminate a reduction in power efficiency at a time of a very light load.
An existing switching power source device includes the kind of current resonant type converter shown in FIG. 18. In this current resonant type converter, an input direct voltage Vi is applied to a series resonant circuit which includes a resonant inductor Lr and a resonant capacitor Cr. By turning two main switch elements Qa and Qb which are configured as metal-oxide-semiconductor field-effect transistors (MOSFET), or the like, ON and OFF, it is possible to control a path of a primary side current flowing in a first coil L1 of a power converting transformer T, so that a current with a sinusoidal waveform flows in the first coil L1 of the transformer T. Also, rectification diodes D1 and D2, which rectify induced secondary currents Is1 and Is2 respectively, and an output capacitor C0, which smoothes an output voltage V0 to a load LD, are connected to a second coil L2 and a third coil L3 of the transformer T (wherein a coil ratio of L1:L2:L3 is taken to be n:1:1).
Furthermore, the output voltage V0 to the load LD is returned to a drive circuit 3 for turning the main switch elements Qa and Qb ON and OFF, via an error amplifier 1 and a voltage control oscillation circuit (VCO) 2. This controls a current and voltage flowing in the first coil L1 of the transformer T, and controls the output voltage V0 at a constant voltage.
The VCO 2 functions in such a way that, when the output voltage V0 of the error amplifier 1, is higher than a set voltage, or is a light load, it increases an output frequency thereof, while when determining that the output voltage V0 is lower than the set voltage, or is a heavy load, it reduces the output frequency thereof.
However, when using this kind of switching power source device as a low voltage, high current power source, the secondary currents Is1 and Is2 flow to the rectification diodes D1 and D2 provided on the secondary side of the transformer T. At this time, a large power loss VF×IO occurs due to a falling forward voltage VF of the rectification diodes D1 and D2. IO indicates a current value of either one of the secondary currents Is1 and Is2.
Therein, in a current resonant type converter shown in FIG. 19, a separately excited drive type of current resonant circuit is used in which MOSFETs Qs1 and Qs2, each of which has a low on resistance, are connected as synchronous rectification switch elements in place of the rectification diodes D1 and D2, a synchronous rectification is carried out, and the above-mentioned power loss is reduced. The MOSFETs Qs1 and Qs2 of FIG. 19 being individually ON-OFF controlled by the drive circuit 3 in synchronization with an operation frequency fop, which turns ON and OFF the primary side main switch elements Qa and Qb, the secondary currents Is1 and Is2 are alternately accumulated in the capacitor C0.
Herein, discussion will be given with respect to separately excited drive synchronous rectification in the current resonant type converter of FIG. 19. In this arrangement the secondary side rectification diodes D1 and D2 in FIG. 18 are replaced with the MOSFETs Qs1 and Qs2, which have a low on resistance.
Synchronous rectification methods, include a self excitation drive method and a separate excitation drive method. Regarding the separate excitation drive method, inasmuch as it emits a drive signal in a logic circuit, by building the logic circuit into a power source IC, it is relatively easy for a power source maker to realize a synchronous rectification function. Consequently, all IC makers tend to devise various separate excitation drive methods (refer to U.S. Pat. No. 7,184,280, U.S. Patent Application Publication No. 2008/0055942, U.S. Patent Application Publication No. 2005/0122753, JP-A-2005-198438, and JP-A-2005-198375, to be described hereafter).
As this kind of heretofore known switching power source device is configured in such a way as to cause a switching operation of the main switch elements Qa and Qb, and obtain an optional direct current output via the voltage converting transformer T, depending on a size of the load LD connected to the secondary side, and the like, a charge accumulated in the capacitor C0 is discharged and a current flowing back to the transformer T side (a reverse current) occurs. This causes a power loss in a reverse flow area which creates a shortcoming.
When considering separate excitation drive synchronous rectification, it will be presumed that it is sufficient that synchronous drive signals of the MOSFETs Qs1 and Qs2 are synchronized with the gate signals which switching control the main switch elements Qa and Qb. However, in actual practice, unless a reverse flow area is detected in each operational mode, and a conversion made to a drive signal synchronized with each one, the charge accumulated in the output capacitor C0 is discharged, a current flowing back to the transformer T side (a reverse current) occurs, and a drop in efficiency occurs. Furthermore, there also emerges a danger of circuit breakage/damage due to the power flowing back to the primary side.
In the current resonant type converter of FIG. 19, the transformer T of the current resonant type converter of FIG. 18 is shown divided into an exciting inductance element Lm and an ideal transformer Ti. The operating principle thereof is clearly illustrated. Herein, prior to a description of the heretofore mentioned power loss in the reverse flow area, a description will be given of the operating principle of the current resonant type converter.
With the illustrated current resonant type converter, two kinds of basic current resonant frequency fr1 and fr2 are defined, as in the following Expressions (1) and (2). Herein, Lr, Lm, and Cr are taken to be, respectively, an inductance of the resonant inductor Lr, the exciting inductance element of the transformer T, and a capacitance of the resonant capacitor Cr.
                              fr          ⁢                                          ⁢          1                =                  1                      2            ⁢            π            ⁢                                          Lr                ·                Cr                                                                        (        1        )                                          fr          ⁢                                          ⁢          2                =                  1                      2            ⁢            π            ⁢                                                            (                                      Lr                    +                    Lm                                    )                                ·                Cr                                                                        (        2        )            
With the switching power source device of FIG. 19, when there is a supply of power to the load LD, the voltage of the exciting inductance element Lm of the transformer T being clamped at n×(V0+VF) in accordance with the output voltage V0, the exciting inductance element Lm is not involved in the current resonance, and power is supplied to the secondary side by operating at the first resonant frequency fr1 (refer to Expression (1) above) decided by the resonant capacitor Cr and resonant inductor Lr. In this case; a sum of a current Im and a resonant current Ir flowing in the exciting inductance element
Lm, flows as a charge-discharge current to the resonant capacitor Cr. At this time, the operation frequency fop of the main switch elements Qa and Qb is controlled by the VCO 2 so as to stabilize the output voltage V0.
The second resonant frequency fr2 (refer to Expression (2) above) being a resonant frequency when no supply of power is carried out to the load LD connected to the secondary side of the transformer T, as the ideal transformer Ti does not function as a transformer, and the voltage of the exciting inductance element Lm of the transformer T is not clamped, a resonance operation is carried out mainly by the capacitance Cr of the resonant capacitor Cr, the resonant inductance Lr of the resonant inductor Lr, and the exciting inductance element Lm.
Regarding the specific resonance operation of the current resonant type converter, it is possible to consider it as being divided into six operational modes (Modes 1 to 6), as shown in FIG. 20, depending on a relationship between its operation frequency fop and the first resonant frequency fr1 (hereafter simply referred to as resonant frequency), and on the size of the load LD connected to the secondary side of the transformer T.
That is, in FIG. 20, Modes 1 to 3 are cases in which the operation frequency fop is lower than the resonant frequency fr1, while Modes 4 to 6 are cases in which the operation frequency fop is equal to, or higher than, the resonant frequency fr1. Also, there is assumed to be a heavy load (HL) condition in the event that the size of the connected load LD is more than 50% of a rated load (maximum load) of the switching power source device, a light load (LL) condition in the event that the size is 20% to 50%, and a very light load (VLL) condition in the event that the size is less than 20%.
Hereafter with reference to FIGS. 21 to 26, a description will be given of a secondary side current waveform induced via the transformer T in each operational mode.
Herein, the reverse flow area in each operational mode is decided by the relationship between the operation frequency fop and resonant frequency fr1 of the current resonant type converter, and by the load LD. Of these, the operation frequency fop changes depending on circuit parameters and the load condition. However, the resonant frequency fr1 is decided by the size of the resonant capacitor Cr and resonant inductor Lr.
Consequently, although a synchronous rectification, which perfectly synchronizes the kinds of synchronous drive signal Vgs1 and Vgs2 shown in FIG. 19 with a power switching signal of the main switch elements Qa and Qb, is simple, the following five reverse flow areas become a problem, and a countermeasure is needed to eliminate the same.
That is, the switching power source device which turns the two main switch elements Qa and Qb ON and OFF using the gate signals Vga and Vgb respectively, and supplies the secondary currents Is1 and Is2, cannot prevent the secondary currents Is1 and Is2 from flowing back in the first operational mode (Mode 1) shown in FIG. 21, unless it reliably turns OFF each of the synchronous control MOSFETs Qs1 and Qs2 at the timings of a latter half of each half cycle (Top/2) of the switching operation. This is because, as the operation frequency fop and resonant frequency fr1 are in the relationship of fop<fr1 in the first operational mode, even though a resonance operation half cycle (Tr/2) is finished, the half cycle (Top/2) of the switching operation is not yet finished.
Consequently, in the event that the kinds of gate signal Vga and Vgb shown in A and B of FIG. 21 are output as they are as synchronous drive signals Vgs 1 and Vgs 2 Lo the synchronous rectification MOSFETs Qs1 and Qs2 shown in FIG. 19, a reverse flow current flows in this timing area (Range A).
Also, in the case of the second operational mode (Mode 2), in which the operation frequency fop is lower than the resonant frequency fr1, and also, the load LD is in the light load (LL) condition, apart from Range A in which the reverse current occurs shown in FIG. 21, there is also a danger of the reverse current occurring in Range B (an area of a timing immediately after the main switch element Qa or Qb is turned on) shown in FIG. 22. This is because with the current resonant type converter, upon the load LD becoming lighter to an extent, the start (timing) of the resonance operation becomes delayed with respect to a start of the switching operation. Then, an operation is depicted wherein, on the load LD becoming lighter still, the start timing of the resonance operation also becomes increasingly delayed.
In the same way, in the case of the third operational mode (Mode 3), in which the operation frequency fop is lower than the resonant frequency fr1, and also, the load LD is in the even smaller very light load (VLL) condition, the reverse current occurs in Range A and Range B. Then, furthermore, although it is within a half cycle of a resonance cycle Tr shown in FIG. 23, the reverse current also occurs in Range C, which corresponds to an area in which the resonance is finished.
In the case of the fourth operational mode (Mode 4) shown in FIG. 24, the operation frequency fop is equal to or higher than the resonant frequency fr1, and also, the load LD is in the heavy load (HL) condition. In this case there is no danger of the reverse current occurring, because the secondary currents Is1 and Is2 are consecutive.
In the fifth operational mode (Mode 5) shown in FIG. 25, the operation frequency fop is equal to or higher than the resonant frequency fr1, and also, the load LD is in the light load (LL) condition. In this case, the reverse current occurs in Range D (an area of a timing immediately after the main switch element Qa or Qb is turned on).
Also, in the case of the sixth operational mode (Mode 6) of FIG. 26, in which the operation frequency fop is equal to or higher than the resonant frequency fr1, and also, there is the very light load (VLL) condition, the reverse current occurs in Range D shown in FIG. 25. Then, furthermore, the reverse current also occurs at a timing, in an area Range E of a period in which the two main switch elements Qa and Qb are each turned ON, at which no power is supplied to the secondary side. This is because, as an amount of energy fed to the secondary side is small in the very light load (VLL) condition, the resonance operation finishes in a short time.
Consequently, in the event of applying signals synchronized with the gate signals Vga and Vgb (the same signals) as the synchronous drive signals Vgs1 and Vgs2 to the synchronous rectification MOSFETs Qs1 and Qs2, as the reverse current occurs in each of the operational modes 1 to 3, and 5 and 6, it has been necessary to form individual synchronous drive signal Vgs 1 and Vgs 2 signal waveforms in the areas (Ranges A to E) corresponding thereto.
Therein, with the heretofore known switching power source device, there is provided a constant width pulse (CWP) generation circuit which outputs a CWP signal with a pulse width slightly narrower than an ON period of the gate signals Vga and Vgb. This forms the waveforms of the synchronous drive signals Vgs 1 and Vgs2 to the synchronous rectification MOSFETs (for example, refer to U.S. Pat. No. 7,184,280).
That is, when the operation frequency fop is the same as, or higher than, the resonant frequency fr1, the synchronous drive signals Vgs 1 and Vgs2 are synchronized with the gate signals Vga and Vgb, and when the operation frequency fop is lower than the resonant frequency fr1, the synchronous drive signals Vgs 1 and Vgs2 are synchronized with the constant width pulse signal CWP, therefore causing it to finish. Because of this, even in the case of replacing the secondary side rectification diodes D1 and D2 with the MOSFETs Qs1 and Qs2, which have a low on resistance, it is possible to prevent the reverse flow current from the secondary side.
However, with the arrangement described in U.S. Pat. No. 7,184,280, as a timing of a rise of the synchronous drive signals Vgs 1 and Vgs2 is always synchronized with the gate signals Vga and Vgb, it is difficult to prevent the reverse current immediately before the secondary current begins to flow, as in the reverse current area (Range B) in the second operational mode (Mode 2). Also, in the cases of Modes 4 to 6, in which the operation frequency fop is the same as, or higher than, the resonant frequency fr1, in the event that the synchronous drive signals Vgs 1 and Vgs2 are synchronized with the gate signals Vga and Vgb, it is not possible to prevent the reverse current under either the light load (LL) condition or very light load (VLL) condition.
As a different switching power supply device, a method which configures a synchronous rectification MOSFET control circuit, as shown in FIG. 27A, has been considered (for example, refer to U.S. Patent Application Publication No. 2008/0055942). Also, an operation waveform of a voltage or current of each portion thereof is shown in FIG. 27B.
This is a method which compares a drain-to-source voltage (Vds(on)) of a synchronous rectification switch element (MOSFET) with a reference voltage REF in a comparator 510, detects that the synchronous rectification MOSFET, or a body diode thereof, is conductive and, for a period during which the conductivity is detected and a gate signal Vgp is high (H), provides a signal causing the synchronous rectification MOSFET to be turned ON. That is, the method generates a comparison signal Vdsc, which is an output of the comparator 510, in an AND circuit 430, and an AND signal of the gate signal Vgp of the primary side main switch elements Qa and Qb, and outputs them as synchronous drive signals Vgs (that is, Vgs1 and Vgs2), of which the waveform has been formed, to the MOSFETs Qs1 and Qs2 (refer to FIG. 19), which are the synchronous rectification switch elements.
Generally, the drain-to-source voltage Vds of the MOSFET, in a condition in which the MOSFET is turned OFF and a current is flowing in the body diode, is equivalent to a body diode falling forward voltage VF. Taking a source potential as a reference potential, the body diode falling forward voltage VF is exactly −VF. Meanwhile, in the case in which the MOSFET is turned ON, the drain-to-source voltage is a product of the ON resistance of the MOSFET and the current flowing, and a value (an absolute value) thereof which is normally smaller than VF.
The reference voltage REF connected to the comparator 510 firstly, by detecting that a current is flowing in the body diode, allows the synchronous rectification MOSFET to be turned ON, and subsequently, the MOSFET being turned ON, in order that it is possible to cause the synchronous rectification MOSFET to continue to be turned ON even when the drain-to-source voltage Vds is small, the absolute value of the reference voltage REF is made considerably small. Actually, taking noise and the like into consideration, it is necessary to make the absolute value large enough to be able to unfailingly detect that the synchronous rectification MOSFET, or the body diode thereof, is conductive.
However, as shown in FIG. 27B, when the secondary current Is decreases to zero, however small the value of the reference voltage REF is, at some point the product of the on resistance of the synchronous rectification MOSFET and the current flowing will become smaller. When this occurs, a condition is such that the comparison signal Vdsc inverts, the synchronous rectification MOSFET is turned OFF, and a current flows in the body diode, whereon the drain-to-source voltage Vds becomes −VF. Because of this, the comparison signal Vdsc inverts again, and the synchronous rectification MOSFET is turned ON again, as a result of which the comparison signal Vdsc further inverts. Subsequently, as shown in the error area of FIG. 27B, the turning ON and OFF of the synchronous rectification MOSFET is repeated at a high frequency until the secondary current Is is definitely zero.
This oscillation phenomenon becomes more noticeable as the load LD becomes lighter, and the secondary current Is decreases. As such, as a high frequency oscillation is repeated without fail every time the secondary current Is decreases to zero. Accordingly, the arrangement described in U.S. Patent Application Publication No. 2008/0055942 is a method with a problem from the point of view of noise and power conversion efficiency.
As an invention which takes into consideration a conducting voltage of the body diode (internal diode), and sets a turn on threshold value (VTH2), there is the one described in U.S. Patent Application Publication No. 2005/0122753. Herein, as a turn ON timing of the synchronous drive signal is decided only by the conducting voltage of the internal diode, there is a problem in that a malfunction is liable to occur in the dead time set in the primary side gate signals Vga and Vgb. Also, as a threshold value (VTH1) which determines a turn OFF timing is a minute voltage value of around −20 mV, and what is more a negative value, there is a problem in that it is easily affected by noise, and the timing of the OFF operation is rendered unstable.
Also, with a different switching power source device, the primary side resonant current is detected with a current transformer, the exciting current is detected with a secondary side auxiliary coil, and a resonant current detection signal is compared with an exciting current detection signal. A synchronous rectification signal is generated based on a signal detecting whether or not a comparison result signal, a power switching signal, and the resonant current detection signal exceed 0A (for example, refer to JP-A-2005-198438).
With the technology of JP-A-2005-198438, it is possible to solve the reverse flow problem in each non-consecutive mode but, as the ON timing of the synchronous rectification MOSFETs is delayed in the operational modes (Modes 1 and 4) with the heavy load condition, the power efficiency decreases. Moreover, as the current transformer and auxiliary coil are used in the detection circuit, the circuit configuration becomes complex, and so on, it is difficult to design to an appropriate adjusted value, and it is not desirable from a point of view of cost either.
Furthermore, as a synchronous rectification circuit which may prevent the current from flowing in the reverse direction, and a power converter which attempts a reduction in power conversion loss, there is the arrangement described in JP-A-2005-198375. This arrangement compares a synchronous rectification transistor source-to-drain voltage in a comparator circuit and, when detecting a reverse direction current, attempts to prevent it using a switching unit. Herein, although a timing at which the synchronous rectification transistor is turned OFF is decided, there is no mention of a timing at which it is turned ON. Consequently, the arrangement is not effective as a measure for preventing the reverse flow of the current (Ranges B and D) in the second operational mode (Mode 2), third operational mode (Mode 3), fifth operational mode (Mode 5), and sixth operational mode (Mode 6). As such, with the heretofore known switching power source devices, there are none which includes a drive circuit that reliably prevents the reverse flow of the secondary current to the primary side in all of the six operational modes (refer to FIG. 20). For example, a method is also possible whereby, in the third operational mode (Mode 3) and sixth operational mode (Mode 6), the load condition is constantly detected and, when there is a change to the very light load condition, the reverse flow of the current (Ranges C and E) is prevented without turning ON the synchronous rectification MOSFETs. However, this kind of light load condition detection method has the following shortcomings.
One detection method has been to monitor an output signal of an error amplifier 1, and detect the condition of the load connected to the switching power source device. However, this method is not one which detects the load condition pulse by pulse (“pulse” herein means a switching pulse), that is, not one which detects the load condition every time a switching is carried out. Then, as there is a response delay in the error amplifier 1 itself, there inevitably occurs a time delay between a very light load condition actually starting and a condition detection signal to the effect that there is a very light load being emitted so, it not being possible to immediately stop the switching operation of the synchronous rectification MOSFETs. Accordingly, this method does not constitute a fundamental solution to the reverse flow problem. Further, the normal current resonant converter is of a design such as to reduce a frequency fluctuation due to a load fluctuation in a voltage-controlled oscillation circuit (VCO) 2. For this reason, a fluctuation in an error signal from the error amplifier 1 also decreases, it is difficult to reliably detect the load fluctuation, and moreover, it is readily affected by noise.
As another method, it is also possible to monitor the current flowing in the load with a resistor, and detect a light load condition.
However, a problem has occurred wherein not only is it impossible to avoid a reduction in power efficiency due to a power consumption occurring in the resistor provided on the secondary side, but also, depending on the circuit parameter design, the power efficiency decreases considerably by uniformly stopping the synchronous rectification when there is a very light load.
The invention having been contrived bearing in mind these kinds of point, an object thereof is to provide a switching power source device and switching power source control circuit which can reliably prevent a reverse flow of a current in any operational mode, and realize a stable synchronous rectification function, without worsening a power efficiency, at a time of a very light load too.
Further objects and advantages of the invention will be apparent from the following description of the invention.